Why did compilation fail for the F-Tile Ethernet Multirate Altera® FPGA IP Design using a 400GE-4 or 400GE-8 reconfiguration group with partition assignments? - Why did compilation fail for the F-Tile Ethernet Multirate Altera® FPGA IP Design using a 400GE-4 or 400GE-8 reconfiguration group with partition assignments? Description In the F-Tile Ethernet Multirate Altera® FPGA IP GUI, if you choose the 400GE-4 (use FHT PMA) or 400GE-8 (use FGT PMA) reconfiguration group and put partition assignments as below, you might encounter compilation failure. >-- set_instance_assignment -name PARTITION eth_vsip_top_0_400g_0 -to mrip_vsip_0_400g_0|eth_vsip_top_inst -entity eth_mrip_top >-- set_instance_assignment -name PARTITION eth_vsip_top_1_200g_0 -to mrip_vsip_1_200g_0|eth_vsip_top_inst -entity eth_mrip_top >-- set_instance_assignment -name PARTITION eth_vsip_top_2_200g_1 -to mrip_vsip_2_200g_1|eth_vsip_top_inst -entity eth_mrip_top >-- set_instance_assignment -name PARTITION eth_vsip_top_3_100g_0 -to mrip_vsip_3_100g_0|eth_vsip_top_inst -entity eth_mrip_top >-- set_instance_assignment -name PARTITION eth_vsip_top_4_100g_1 -to mrip_vsip_4_100g_1|eth_vsip_top_inst -entity eth_mrip_top >-- set_instance_assignment -name PARTITION eth_vsip_top_5_100g_2 -to mrip_vsip_5_100g_2|eth_vsip_top_inst -entity eth_mrip_top >-- set_instance_assignment -name PARTITION eth_vsip_top_6_100g_3 -to mrip_vsip_6_100g_3|eth_vsip_top_inst -entity eth_mrip_top Resolution Follow the instructions below to work around this problem in the Quartus® Prime Pro Edition software version 24.3. 1). Run more seeds 2). Change the partition inputs so that inputs driven by a global clock are not shared (i.e. for global clock inputs, only have one unique partition input connected to the clock). For example: module instance_name ( input clk1, input clk2, output out ... usage ); endmodule The above module is instantiated similar to the following: instance_name inst ( .clk1 ( clk ), .clk2 ( clk ), .out ( out ) ); If “inst” is used as a user partition (i.e., the PARTITION instance assignment is used on 'inst'), then an RTL workaround would be to 'merge' clk1 and clk2 since the instantiation of the module is done with the same signal for both. i.e.: module instance_name( input clk1_or_2, output out ... usage ); endmodule And is instantiated as: instance_name inst( .clk1_or_2 ( clk ), .out ( out ) ); Custom Fields values: ['novalue'] Troubleshooting 16025026122 False ['F-Tile Ethernet Multirate IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']