EMIF Maximum Frequency Specification Update for Stratix V - EMIF Maximum Frequency Specification Update for Stratix V Description This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Stratix V devices may have difficulty achieving timing closure at certain maximum frequencies. Resolution The workaround for this issue is to apply the appropriate solution for your configuration as described below: For Stratix V , -C1/-C2 speed grade device interfacing with a DDR2 SDRAM DIMM in a quad-rank, dual-slot configuration, using soft controller at half-rate, and a frequency specification of 400 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve the specified maximum frequency. For Stratix V , -C1/-C2 speed grade device interfacing with a DDR2 SDRAM component in a 2-chip select configuration, using soft controller at half-rate, and a frequency specification of 400 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve the specified maximum frequency. This issue will not be fixed. The solutions for maximum frequency specifications will be updated in a future version of the External Memory Interface Spec Estimator. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']