Agilex 7 F-Tile Ethernet Hard IP - The Agilex 7 FPGA F-Tile IP core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The user can choose a media access control (MAC) and a… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series The Agilex 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates from 10G to 400G, compatible with the IEEE 802.3 specification and other related Ethernet Consortium specifications. This intellectual property (IP) core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. It is available in multiple variants providing different combinations of Ethernet channels and features. These include optional Reed-Solomon Forward Error Correction (RSFEC) and optional IEEE 1588v2 Precision Time Protocol (PTP). The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation. This IP core is included in the IP library and is available from the IP Catalog. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Agilex 7 F-Tile Ethernet Hard IP Key Features The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed-length traffic with no dropped packets Offering Brief No No No Yes Encrypted Verilog Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Yes Yes Offering Brief Production a1JUi0000049UUuMAM What's Included Encrypted Verilog source code Ordering Information IP-ETH-F-ANLT Direct a1JUi0000049UUuMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2026-04-21T12:58:34.000+0000 The Agilex 7 FPGA F-Tile IP core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation. Altera Solutions