Arria 10 Hard IP for PCI Express IP Core Gen2 and Gen3 Directed Speed Change Error - Arria 10 Hard IP for PCI Express IP Core Gen2 and Gen3 Directed Speed Change Error Description An intermittent Surprise Link Down or failure to speed change may occur in applications using a software directed speed change. These errors typically occur in less than 1% of the directed speed changes. If your application does not use a directed speed change, there is no impact. Resolution There is no workaround other than avoiding the directed speed change. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']