Transceiver Basics for 20 nm and 28 nm Devices - 54 Minutes High-speed transceiver-based FPGAs are mainstream devices in the programmable logic space today. This online course provides an overview of the transceivers found in transceiver-based Altera® FPGA in the Altera® Quartus® Prime software. By the end of this training, you will be able to define the blocks found in the both the transmitter and receiver data paths along with their purposes. You will also be able to specify which blocks make up the digital physical coding sub-layer (PCS) and the analog physical media attachment (PMA). Targeted devices: Cyclone® IV, Cyclone V, Arria® II, Arria V, Arria 10, Stratix® IV, Stratix V FPGAs Course Objectives At course completion, you will be able to: Describe the blocks found in the transmitter and receiver paths of FPGA high-speed serial transceivers Define which blocks make up the physical coding sub-layer and which make up the physical media attachment Skills Required Background in digital logic General understanding of FPGA architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OSIIGX1115. FPGA_OSIIGX1115. <p>Transceiver Basics for 20 nm and 28 nm Devices</p>