Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset - Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset Dear Intel, Based on the forum info and datasheet it is allow to use soft reset rather than hard reset. In order to do so, changing <parameter name="force_src" value="0" /> to <parameter name="force_src" value="1" /> Should basically turn the HRC to SRC. However during actual system test SRC stuck on driver loaded while HRC does not. According to the above background informations: 1: do SRC allowed in GEN1 PCIe 2: How to properly driven the reset signal under verilog possible example could be good. Thanks, Brian Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset Ok the solution to resolve SRC under Hard PCIe RP: The example from rocketchip and MitySOM gate the mgmt reset by nreset_status. Due to pin_perst is not used -> 1'b1 The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset by nreset_status will dead lock and never exit the reset. Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset I was not aware of this is a RP use case so my previous suggestions were not aligned to your needs. I noticed you have another similar topic in the forum with better statement. https://community.altera.com/discussions/fpga-device/avalon-mm-cyclone-v-hard-ip-for-pci-express-intel-fpga-ip---hard-reset-to-soft-r/350590 To prevent duplicate threads on the same issue, this topic will be closed. Thanks for your understanding. Regards, Rong Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset RongY_altera I am amazed how can you run lspci when root port not even exist? Maybe another Altera staff can help this ticket? Feels like you are not well understand the entire PCIe system. And stop quoting useless stackexchange this is completely not related this ticket nor what it is asking. Thanks Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset "Once confirming PCIe link info correctly in lspci, you can try rescan and reset commands by referencing https://unix.stackexchange.com/questions/73908/how-to-reset-cycle-power-to-a-pcie-device" >>These are Linux commands to test your PCIe. No need to load driver. Regards, Rong Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset RongY_altera Can you read carefully previous posts? BrianSune_Froum wrote: The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load. This is referring to the PCIe itself not slot card nor end-point devices. You are not even able to type any thing as it stuck or hang once the pcie-altera.ko insert. Thanks Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset Normally you need to follow the PCIe user guide to set hip_hard_reset_hwtcl to 0. I think you have done that and you're able to boot into Linux. Once confirming PCIe link info correctly in lspci, you can try rescan and reset commands by referencing https://unix.stackexchange.com/questions/73908/how-to-reset-cycle-power-to-a-pcie-device Regards, Rong Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset RongY_altera Can you read previous posts? I am not focusing on npor problem The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load. Where the HRC case did not have such issue. Thanks Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset Hi Brian, By using SRC you're likely to control the npor. If so, you need to pull npor LOW more than 100ms and only release it when PCIe ref clock is stable. Regards, Rong Replies: Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset Hi Altera, More info: Based on the STLA, it looks like the reconfiguration calibration never turn low after reset. While HRC can work without any issue. The SRC simply feed 1'b1 to the pin_perst and please do help or provide instruction to fix this trouble. Thanks, Brian