Why does the Nios development board reset after I program my design into the Altera FGPA? - Why does the Nios development board reset after I program my design into the Altera FGPA? Description One reason this can happen is because the unused pins in the FPGA design are not tri-stated. Make sure you have the unused pins for your Quartus II project set to be Inputs Tristated. You can do this as follows in the Quartus II tool: Click on Assignments -> Device Click on the Device and Pin Options button Click on the Unused Pins tab. Click on the As inputs, tri-stated radio button Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']