Why do I get uncorrectable FEC errors or ‘o_rx_pcs_ready’ signal low during reset testing for F-Tile Ethernet FPGA Hard IP variant for PAM4 designs with FEC enabled? - Why do I get uncorrectable FEC errors or ‘o_rx_pcs_ready’ signal low during reset testing for F-Tile Ethernet FPGA Hard IP variant for PAM4 designs with FEC enabled? Description When using some optic modules, you may see uncorrectable FEC errors or ‘o_rx_pcs_ready’ signal low during reset testing for F-Tile Ethernet Intel FPGA Hard IP variant for PAM4 links with FEC enabled. Resolution The workaround for this problem is to understand the link settling time for the module and increase the delay before checking the link. You may need to issue another reset to recover the link. Custom Fields values: ['novalue'] Troubleshooting 15016214274, 16024845948 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']