Why does the Intel® Stratix® 10 Chip ID IP core read all zeros in user mode? - Why does the Intel® Stratix® 10 Chip ID IP core read all zeros in user mode? Description When the Intel® Stratix® 10 Chip ID IP core is taken out of reset in user mode, you may see no output on the 'chip_id' port even after the assertion of 'data_valid' signal. This may be seen with designs compiled in Intel Quartus® Prime Pro software version 17.1. Resolution To read out the unique chip ID from Intel Stratix 10 devices Assert reset initially to reset the chip ID IP core. Trigger a high -> low transition on the 'readid' port to initiate one read command to the IP core. Use the 'readid' port to trigger multiple reads in user mode. This problem has been fixed in Intel Quartus Prime Pro software version 18.0. Custom Fields values: ['novalue'] Troubleshooting FB: 554718; False ['Chip ID Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']