Is en_pfc_port in E-Tile Ethernet IP a read only register? - Is en_pfc_port in E-Tile Ethernet IP a read only register? Description Due to a problem in E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs (UG-20160), en_pfc_port register is wrongly defined as ready only. In fact, it is a read-write register to enable TX PAUSE or TX PFC. Resolution This problem is currently scheduled to be fixed in a future release of the UG-20160. Custom Fields values: ['novalue'] Troubleshooting 15014771343 False ['novalue'] ['novalue'] novalue novalue ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']