Why is there a mismatch on the write and read data between the AXI bus interface and the Intel® Stratix® 10 MX HBM2 simulation model messages during simulation? - Why is there a mismatch on the write and read data between the AXI bus interface and the Intel® Stratix® 10 MX HBM2 simulation model messages during simulation? Description The mismatch occurs because the write data from the AXI bus interface goes into the Intel® Stratix® 10 MX HBM2 IP's soft adapter and through the Universal Interface Block Subsystem before it reaches the Intel® Stratix® 10 MX HBM2 memory model. Resolution The "write data" bus value reported in the HBM2 memory model has been modified due to the data bus inversion (DBI). Custom Fields values: ['novalue'] Troubleshooting 1506982144 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']