How can I enable the use of the Txs slave port of PCIe Avalon-MM interface? - How can I enable the use of the Txs slave port of PCIe Avalon-MM interface? Description To enable the use of the Txs slave port, the Master Enable bit (bit 2) in the PCIe ® configuration space register at offset 0x4 has to be set to '1' via the CRA interface. (It is also observed at bit 2 of cfg_prmcsr). Without setting Master Enable bit to '1', TxsWaitRequest_o signal stays at '1' and it does not accept read and write transactions. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']