Introduction to Hyper-Optimization - 22 Minutes Are you targeting an Agilex™ series or Stratix® 10 FPGA and wanting to learn how your design can reach the maximum core performance? This course will give you an introduction to advanced optimization techniques that can be useful when targeting Altera® FPGAs equipped with the HyperFlex™ architecture. In this course, you will learn about design practices that limit the effectiveness of Hyper-Retiming and Hyper-Pipelining and about Hyper-Optimization tools and techniques that can be used to to overcome those bottlenecks, allow you to achieve the full potential of the Hyperflex architecture. Course Objectives At course completion, you will be able to: Understand factors that may Reduce the effectiveness of Hyper-Retiming and Hyper-pipelining Locate and evaluate loop structures that Reduce design performance using the Fast Forward analysis feature of the Altera® Quartus Prime Pro software Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus® Prime Pro software Familiarity with Verilog or VHDL synthesizable design structures If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10HYPOPT. FPGA_OS10HYPOPT. <p>Introduction to Hyper-Optimization</p>