Why do I see a low restricted fmax when using a floating-point adder in Arria 10 DSP block, either with OpenCL or DSP Advanced Blockset? - Why do I see a low restricted fmax when using a floating-point adder in Arria 10 DSP block, either with OpenCL or DSP Advanced Blockset? Description This problem affects designs targeting Arria 10 DSP blocks’ floating-point mode and when you implement the floating-point adder in DSP blocks. The specification for the adder when fully pipelined is to operate at over 450MHz. However, in the Quartus II software v15.0, you see a restricted fMAX of 298.51 MHz for this module. Resolution This problem is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']