Why do I see RTS and CTS signal in U-boot when using both UART0 and I2C1 on the same pin with Auto Flow control disabled on Cyclone® V SoCs? - Why do I see RTS and CTS signal in U-boot when using both UART0 and I2C1 on the same pin with Auto Flow control disabled on Cyclone® V SoCs? Description When using UART0 and I2C1 on Cyclone® V SoCs, you might observe that the msr.dcts register value changed in U-boot with Automatic Flow Control disabled in your Platform Designer system when reading or writing using I2C. Resolution The changed in msr.dcts register value can be safely ignored. Custom Fields values: ['novalue'] Troubleshooting 15010890905 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 22.4 21.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['Cyclone® V FPGA Dev Kit']