What can cause the fPLLs to not function properly in Stratix V, Arria V, or Cyclone V devices? - What can cause the fPLLs to not function properly in Stratix V, Arria V, or Cyclone V devices? Description The fPLLs in Stratix® V, Arria® V, and Cyclone® V devices require the RREF pin(s) to be connected to GND through a precision resistor in order to function properly. If the RREF pin(s) are tied directly to GND or left floating, some or all of the fPLLs may fail to function. Resolution Refer to the Device Pin Connection Guidelines for the device you are using for specific guidance on how to connect the RREF pins. You can also refer to Possible Causes for PLL Loss of Lock . Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']