Why are the Low Latency 40G/100G Ethernet IP pause timers off by a factor of two? - Why are the Low Latency 40G/100G Ethernet IP pause timers off by a factor of two? Description Due to a problem with the Intel® Low Latency 40G Ethernet IP core, you will see the pause counters increment twice as fast as expected. You will see this behavior for both Standard Flow Control and Priority Flow Control modes. Resolution This problem has been fixed in the Intel Quartus® Prime version 16.0 software. Custom Fields values: ['novalue'] Troubleshooting FB: 366690; True ['Ethernet', 'Low Latency 40G 100G Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 13.1.3 ['Arria® 10 FPGAs and SoCs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']