Why does the F-Tile variant with a combination of PTP and non-PTP enabled ports within the Ethernet Subsystem FPGA IP fail to simulate correctly? - Why does the F-Tile variant with a combination of PTP and non-PTP enabled ports within the Ethernet Subsystem FPGA IP fail to simulate correctly? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, the F-Tile variants with a combination of PTP and non-PTP enabled ports within the Ethernet Subsystem FPGA IP will fail to simulate properly. Resolution There is no workaround for this problem. This problem had been fixed in version 24.2 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16020482108, 16021065490 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']