Why do the 25G Ethernet Intel® Arria® 10 FPGA IP core, Intel® 50 Gbps Ethernet (50GbE) IP core, and the 25G Ethernet Intel® Stratix® 10 FPGA IP core incorrectly report oversized frames for VLAN and Stacked VLAN Tagged frames? - Why do the 25G Ethernet Intel® Arria® 10 FPGA IP core, Intel® 50 Gbps Ethernet (50GbE) IP core, and the 25G Ethernet Intel® Stratix® 10 FPGA IP core incorrectly report oversized frames for VLAN and Stacked VLAN Tagged frames? Description Due to a problem with the IP Cores listed above, oversized frames are incorrectly reported to VLAN/Stacked VLAN tagged frames when all conditions below are met: VLAN frame VLAN Detection is enabled Sending/receiving frame length is between the maximum TX/RX frame length plus 1 to 4 octets Stacked VLAN frame VLAN Detection is enabled Sending/receiving frame length is between the maximum TX/RX frame length plus 1 to 8 octets Resolution No workaround for this problem exists in current releases of the IP. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 20.4. Custom Fields values: ['novalue'] Troubleshooting 1508321260 True ['25G Ethernet IP', '50G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 20.4 19.4 ['Arria® 10 GT FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']