Reducing Compile Time with Fast Preservation - Same Course in Japanese: 高速保存によるコンパイル時間の短縮 46 Minutes Everybody wants to reduce their compile times. Whether debugging or optimizing a design to meet timing, you want to get back to testing and working with the design as quickly as possible. With the Fast Preservation feature enabled, you can exponentially reduce compile times in the Altera® Quartus® Prime Pro edition software when using a block-based design flow, such as design block reuse or partial reconfiguration (PR). This training shows you how to set up your project to make use of this feature whether you are already using a block-based design flow or not. Basic required concepts, such as design partitioning and floorplanning with Logic Lock regions are reviewed, but see the recommended prerequisites for more details. Course Objectives At course completion, you will be able to: Know the advantages of using the Fast Preservation feature in a block-based design flow Set up a design to make use of the feature to greatly Reduce compile times Skills Required Background in digital logic design Familiarity with the Altera® Quartus® Prime software Familiarity with the main block-based design flows: partial reconfiguration, design block reuse, or incremental block-based compilation If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OFASTPRES. FPGA_OFASTPRES. <p>Reducing Compile Time with Fast Preservation</p>