MAX 10 I/O pin current during configuration - MAX 10 I/O pin current during configuration The MAX 10 data sheet states that the range of the "weak pull-up" for 1.8V banks is between 16K to 75K. I am seeing around a 250ua or a 1.8K equivalent resistance during configuration. Where can I learn more about what to expect for the MAX 10's I/O pins during configuration? Can anyone help? Replies: Re: MAX 10 I/O pin current during configuration Hello, Thank you for using Intel FPGA. I can list down documents that you can refer to for your FPGA designs below: 1. Intel® MAX® 10 FPGA Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf 2. Intel® MAX® 10 General Purpose I/O User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf 3. Intel Max 10 FPGA Device Family Pin Connection Guidelines: https://www.intel.com/content/www/us/en/programmable/documentation/luo1479889762304.html 4. Pin-Out Files for Intel FPGA: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html There is also How To Video on Youtube that you can refer to. I hope these documents can help you understand Intel Max 10 better.