Why does the FIFO FPGA IP GUI not produce any error message when the Enable Error Checking and Correcting (ECC) option is selected? - Why does the FIFO FPGA IP GUI not produce any error message when the Enable Error Checking and Correcting (ECC) option is selected? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, the Details tab in the GUI incorrectly states for the Enable error checking and correcting (ECC) option, "This option is only available for Arria® 10 FPGA devices using M20K memory block type". This is incorrect, and this option is supported for all device families that support M20K memory block types. When this option is selected, and the device selected is not an Arria® 10 FPGA, no error message is generated in the FIFO FPGA IP Parameter Editor GUI. Resolution There is no workaround necessary. The ECC feature is supported in any family device using the M20K memory block type. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 16025508054 False ['FIFO IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.2 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']