Why do some I/O pins of Intel® MAX® 10 devices 10M04SAU324I7G and 10M04SCU324C8G stay low rather than tri-state with pull up during normal ISP? - Why do some I/O pins of Intel® MAX® 10 devices 10M04SAU324I7G and 10M04SCU324C8G stay low rather than tri-state with pull up during normal ISP? Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.0, some I/O pins of Intel® MAX® 10 devices 10M04SAU324I7G and 10M04SCU324C8G will remain low rather than tri-state with pull-up during normal ISP. This is related to a previous known problem, described in Why do I observe some I/O pins being driven to LOW (GND) during the POF file programming for MAX 10 devices? Resolution This problem is fixed in Intel® Quartus® Prime Standard Edition Software version 19.1. Custom Fields values: ['novalue'] Troubleshooting 1507141880 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 19.1 18.0 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']