Why does the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP fail to respond to inbound memory read TLPs with the Relaxed Ordering bit set? - Why does the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP fail to respond to inbound memory read TLPs with the Relaxed Ordering bit set? Description Due to a limitation of the Intel® Stratix® 10 PCIe* Avalon® -MM Bridge, inbound memory read TLPs with the Relaxed Ordering bit set will be dropped and no completion returned , which can cause system failure. Resolution To work around this problem, constrain the link partner to only send the Memory read TLPs without the Relaxed Ordering bit set to the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP. Custom Fields values: ['novalue'] Troubleshooting 2205693312 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']