Why UART1.RTS_N and UART1.CTS are missing in exported ports on Intel® Arria® 10 HPS Dedicated I/O? - Why UART1.RTS_N and UART1.CTS are missing in exported ports on Intel® Arria® 10 HPS Dedicated I/O? Description Due to a problem in the Intel® Quartus® Prime Edition Software version, you cannot assign UART pin assignments below on Intel® Arria ® 10 HPS Dedicated I/O. 13:UART1:RTS_N 14:UART1:CTS_N 16:UART1:TX 17:UART1:RX Resolution Use alternative pin assignments below to work around this problem in the Intel® Quartus® Prime Pro/Standard Edition Software versions. 12:UART1.TX 13:UART1:RTS_N 14:UART1:CTS_N 15:UART1:RX However, if you cannot assign the above assignment, follow the steps below . 1. Create a design on Platform Designer with UART pin assignments below on HPS Dedicated I/O, and generate RTL. 12:UART1.TX 13:UART1:RTS_N 14:UART1:CTS_N 15:UART1:RX 16:NONE 17:NONE 2. Compile the design on Quartus 3. Open hps_isw_handoff/hps.xml. Pin 12 and 15 are updated to NONE. Pin 16 and 17 are updated to UART1.TX and UART1.RX. All bold text is updated. <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_12.sel' value='10' /> <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_13.sel' value='13' /> <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_14.sel' value='13' /> <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_15.sel' value='10' /> <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_16.sel' value='13' /> <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_17.sel' value='13' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pu_drv_strg' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pd_drv_strg' value='0' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.wk_pu_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pu_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pd_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pd_drv_strg' value='10' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.input_buf_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.wk_pu_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pu_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pd_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pd_drv_strg' value='10' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pu_drv_strg' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pd_drv_strg' value='0' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.wk_pu_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pu_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pd_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pd_drv_strg' value='10' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.input_buf_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.wk_pu_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pu_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pd_slw_rt' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pd_drv_strg' value='10' /> This problem will be fixed in a future release of the Intel® Quartus® Prime Edition Software. Custom Fields values: ['novalue'] Troubleshooting 1408166616 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 18.1 ['Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']