JESD204B IP Core ed_synth Timing Failure (Arria V) - JESD204B IP Core ed_synth Timing Failure (Arria V) Description The JESD204B IP core design example has a hold time violation to the transceiver. This issue affects all versions that support the JESD204B IP core. Resolution You can use the set_min_delay command to change the absolute minimum delay for the path. The value to apply depends on the negative slack that you see. For example, in a case where the negative slack = –0.04, apply a value of 0.1 ns (with around 0.06 ns as the guardband). if {$::quartus(nameofexecutable) == "quartus_fit"} { set_min_delay -to [get_keepers {*inst_av_hssi_8g_tx_pcs|wys~BURIED_SYNC_DATA*}] 0.100ns } Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']