Why is waitrequest still high after readdatavalid is asserted in ASMI Parallel II Intel® FPGA IP? - Why is waitrequest still high after readdatavalid is asserted in ASMI Parallel II Intel® FPGA IP? Description Due to a problem with the ASMI Parallel II Intel® FPGA IP, you will see this behavior if the read signal is asserted when the IP is stalling a new command with waitrequest high. The readdatavalid signal will be asserted one clock cycle after the read signal is asserted. Because the IP is still busy, waitrequest stays high. The readdata bus from the IP is not valid. Resolution To work around this problem, do not send the read command to the IP when the waitrequest is high. Send the read command when waitrequest signal is deasserted. Custom Fields values: ['novalue'] Troubleshooting 2205689365 False ['ASMI Parallel II IP', 'Avalon-MM Pipeline Bridge IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.0 ['Programmable Logic Devices'] ['novalue'] ['Configuration Device EPCQ', 'Configuration Device EPCQ-A', 'Configuration Device EPCQ-L', 'Configuration Devices', 'Configuration Device EPCQ', 'Configuration Device EPCQ-A', 'Configuration Device EPCQ-L', 'Configuration Devices'] ['novalue']