Internal Error: Sub-system: ASMPLL, File: /quartus/comp/asmpll/asmpll_28nm.cpp, Line: 231 - Internal Error: Sub-system: ASMPLL, File: /quartus/comp/asmpll/asmpll_28nm.cpp, Line: 231 Description Due to a problem in the Quartus® II software version 12.0, you may see this error if your HDL code implements a PLL in normal or source-synchronous mode and drives an external clock output. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices. Resolution To work around this problem, do not use normal or source-synchronous mode and an external clock output at the same time. The issue is fixed beginning with the Quartus II software version 12.0 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 12.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']