SOC-09 - Embedded Linux Development for Altera® SoCs - 3 Days - Enroll Now This course is the definitive program for engineers who need to master the complete Embedded Linux software stack on Altera® SoC FPGA platforms. Students progress systematically from the fundamentals of the Hard Processor System (HPS) architecture, through every stage of the boot chain (BootROM, FSBL/SPL, ARM Trusted Firmware, U-Boot), across the Linux kernel and device tree layer, through Yocto-based root filesystem construction, into FPGA fabric integration and custom Linux driver development, and finally to advanced topics including boot-time optimization, runtime performance profiling, secure boot, long-term BSP maintainability, and CI/CD integration. Course Content: 1. Altera® SoC FPGA Family Overview 2. Hard Processor System (HPS) Architecture Deep Dive — Cortex A Cores, L2 Cache, MMU 3. FPGA Fabric and HPS-FPGA Interface Architecture 4. Bridge Topology — AXI HPS-to-FPGA, FPGA-to-HPS, Lightweight, and SDRAM Bridges 5. Multi Stage Boot Sequence Overview — BootROM → SPL → ATF → U-Boot → Linux 6. BSP Development Workflow, and Toolchain Introduction 7. Yocto Project Concepts — Layers, Recipes, BitBake, and the meta-altera-fpga Layer 8. BootROM Internals — Boot Modes, RBF Header Parsing, and Handoff to SPL 9. Secondary Program Loader (SPL) / FSBL Architecture and Source Code Structure 10. DDR Memory Initialization — PHY Calibration, Timing Parameters, and Error Handling 11. Clock and PLL Configuration in the SPL — HPS PLL Map and bsp-editor Integration 12. Generating and Customizing the SPL with Altera BSP Editor and Yocto 13. ARM Trusted Firmware (ATF) — BL1, BL2, BL31, Secure Monitor, and PSCI 14. Secure Boot Architecture — Key Provisioning, Chain of Trust, and Device Lifecycle 15. U-Boot Architecture — Source Tree, Board Configuration Files, and Command Set 16. U-Boot Build System — Kconfig, defconfig, and the Yocto meta-altera-fpga Recipe 17. Hardware/Software Handoff from Quartus Prime and Platform Designer 18. Clock and Reset Management Across the Handoff Boundary 19. FPGA Configuration Methods from U-Boot — FPGA Load, fpga loadmk, and RBF Files 20. U-Boot Environment Variables — persistent storage, import/export, and scripting 21. U-Boot Boot Scripts — bootcmd, extlinux.conf, distro_bootcmd, and FIT Images 22. Linux Kernel Source Tree Structure for Altera SoC Targets 23. Kernel Configuration — defconfig, menuconfig, and Configuration Fragments 24. Altera Kernel Patches and the meta-altera-fpga Kernel Recipe (linux-altera lts) 25. Kernel Build Artefacts — zImage, Image, uImage, DTB, and Modules 26. Kernel Deployment — TFTP/NFS for Development, eMMC/SD for Production 27. Early Boot Debugging — earlycon, earlyprintk, initcall_debug, and loglevel 28. Kernel Version Management and Long Term Support (LTS) Strategy 29. Device Tree Fundamentals — Purpose, Structure, and Compilation 30. DTS / DTSI Syntax — Nodes, Properties, Phandles, and Includes 31. Device Tree Bindings — The Contract Between DTS and Kernel Drivers 32. Reference Device Trees for Cyclone V, Arria 10, and Agilex Development Kits 33. HPS Peripheral DTS Nodes — UART, I2C, SPI, EMAC, USB, GPIO, SDMMC 34. Generating and Customizing the SoC FPGA Device Tree with sopc2dts 35. Mapping FPGA IP Cores to DTS Nodes — reg, interrupts, and custom properties 36. Device Tree Overlays — Syntax, Compilation, and Runtime Application 37. Yocto Project Architecture — BitBake Execution Model, Tasks, and Signatures 38. Layer Structure — bblayers.conf, layer.conf, and Priority Resolution 39. meta-altera and meta-altera-fpga Layer Structure and Machine Definitions 40. Machine Configuration — MACHINE Variables, SOC_FAMILY, and Preferred Versions 41. Writing and Extending Recipes — .bb, .bbappend, SRC_URI, and do_ Tasks 42. DISTRO Configuration — Feature Flags, PACKAGECONFIG, and Systemd vs SysVinit 43. Dependency Management — DEPENDS, RDEPENDS, and PROVIDES 44. Yocto Image Recipes — Anatomy of core-image-minimal and IMAGE_FEATURES 45. Package Groups — packagegroup-core-, Custom Groups, and Feature Composition 46. Package Management — ipk, rpm, deb Backends and Runtime Package Feeds SDK Generation — Standard SDK, eSDK, and Cross Development Workflow Custom Application and Library Recipes — Autotools, CMake, and Meson Integration 49. Root Filesystem Optimization — Size Reduction, Unused Package Pruning 50. Deployment Strategies — eMMC/SD, initramfs, OverlayFS, and Read Only rootfs 51. HPS-to-FPGA and FPGA-to-HPS Bridge Architecture and Register Map 52. Bridge Enable/Disable Sequences and Linux FPGA Manager Subsystem 53. Runtime FPGA Reconfiguration — Full Reconfiguration and PR Regions (dfb) 54. Userspace FPGA Access — devmem, /dev/mem mmap, and UIO Framework 55. Linux Platform Driver Model — Probe, Remove, and Device Tree Matching 56. Writing a Character Device Driver for a Memory Mapped FPGA AXI Peripheral 57. DMA for FPGA Peripherals — DMA Engine API, Scatter Gather, and Cache Coherency 58. Interrupt Handling for FPGA IP — IRQ Registration, Threaded IRQs, and Latency 59. Debugging SPL and U-Boot — JTAG, Serial Log Levels, and Ashling RiscFree IDE 60. Kernel and Driver Debugging — ftrace, dynamic_debug, and printk Levels 61. KGDB and KGDBOC — Source Level Kernel Debugging over Serial and Network 62. Kernel Oops and Panic Analysis — Stack Trace Decoding with addr2line and objdump 63. Boot Time Analysis — systemd-analyze, Bootchart, and Service Dependency Graphs 64. Boot Time Reduction Techniques — Parallel Init, Lazy Loading, and initramfs 65. RAM Filesystem (initramfs) vs. eMMC/SD Root Filesystem Trade offs 66. Runtime Performance Profiling — perf, ftrace, LTTng, and the Yocto Perf Layer 67. Secure Boot Architecture for Altera SoCs — Chain of Trust and Key Hierarchy 68. Key Generation, Provisioning, and Device Lifecycle Management 69. Signed FIT Images — mkimage, U-Boot Verified Boot, and SPL Signature Verification 70. Altera Security Manager and Bitstream Authentication 71. TrustZone and OP-TEE Introduction for AArch64 Agilex Platforms 72. BSP Layer and Dependency Management — kas, devtool, and Workspace Mode 73. Reproducible Builds — SSTATE_MIRROR, Shared State Cache, and BB_HASHBASE_WHITELIST 74. CI/CD Integration — GitLab CI / GitHub Actions Pipelines with Yocto and Docker 75. Software Licence Compliance — LIC_FILES_CHKSUM, SPDX Reports, and FOSS Obligations 76. CVE Patch Management and Long Term BSP Security Maintenance Prerequisites: - Proficiency with the Linux command line — filesystem navigation, shell scripting, make, and package managers - Basic embedded software development experience — cross compilation, flashing targets, serial debug - Working knowledge of C programming and software compilation concepts - Conceptual understanding of embedded systems — processors, memory maps, and peripherals - Completion of the FPGA Authority 'Introduction to Altera SoC FPGAs' course, or equivalent hands-on HPS configuration experience in Quartus Prime Software Recommended (beneficial but not strictly required): - Familiarity with ARM Cortex A processor architecture and the ARMv7/ARMv8 memory model - Exposure to U-Boot or other embedded bootloaders - Experience with Quartus Prime and Platform Designer (Qsys) for HPS IP configuration - Familiarity with device tree syntax and ARM SoC peripheral description conventions - Introductory Yocto Project or Buildroot exposure - Basic knowledge of Linux kernel modules or driver development - Experience with Git for version control Tools Required: - Quartus Prime Software Pro / Standard Edition - Ashling RiscFree IDE for Altera FPGAs - Programmer / JTAG Tools - Yocto Project / BitBake - U-Boot - Linux Kernel - ARM Trusted Firmware (ATF) - ARM GNU Toolchain (arm-linux-gnueabihf / aarch64-linux-gnu) - TFTP / NFS Server - minicom / PuTTY - Docker (optional) - Visual Studio Code Course code: SOC-09. FA_SOC2.