RapidIO II IP Core Logical/Transport Layer Error Detect Register Does Not Behave as Documented - RapidIO II IP Core Logical/Transport Layer Error Detect Register Does Not Behave as Documented Description The RapidIO II IP core Logical/Transport Layer Error Detect CSR (offset 0x308) should indicate detected errors only for error types that are enabled in the Logical/Transport Layer Error Enable CSR (offset 0x20C). However, the Logical/Transport Layer Error Detect CSR detects errors irrespective of the corresponding enable settings. In addition, the Logical/Transport Layer Error Detect CSR should not support the clearing of individual bits. However, user logic can clear the register bits individually. Resolution This issue has no workaround. This issue is fixed in version 14.0 of the RapidIO II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']