How can I change Base Address Register(BAR) Size when using the Avalon -MM Intel® Arria® V Hard IP for PCI Express* Intel® FPGA IP or the Avalon -MM Cyclone® V Hard IP for PCI Express* Intel® FPGA IP? - How can I change Base Address Register(BAR) Size when using the Avalon -MM Intel® Arria® V Hard IP for PCI Express* Intel® FPGA IP or the Avalon -MM Cyclone® V Hard IP for PCI Express* Intel® FPGA IP? Description When using the Avalon -MM Intel® Arria® V Hard IP for PCI Express* Intel® FPGA IP or the Avalon -MM Cyclone® V Hard IP for PCI Express* Intel® FPGA IP, the BAR size in the GUI may appear fixed and set at "N/A." The BAR size when using Avalon - MM configuration of the IP is automatically set by Platform Designer and is not manually set by the user. Resolution To correctly set the required BAR size: First, add the I P to Platform Designer and enable any required BAR Registers. Second, in Platform Designer, connect the BAR Register ports to the required other components within the design. If the PCIe* IP is then re-opened, you will see that the BAR size has been automatically set based on the connected components. The BAR size cannot be manually set by the user. Custom Fields values: ['novalue'] Troubleshooting FB: 1408179861; False ['Arria® V Hard IP for PCI Express IP', 'Cyclone® V Hard IP for PCI Express IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']