DDR2 and DDR3 SDRAM Controller with UniPHY Example Design Fails as a Slave - DDR2 and DDR3 SDRAM Controller with UniPHY Example Design Fails as a Slave Description In slave mode, the MegaWizard interface instantiates the PLL in the example_top.v file. However for DDR2 and DDR3 SDRAM example designs, the wizard fails to connect the DQS enable clock to the PLL. Resolution To work around this issue, modify example_top.v to connect the DQS enable clock (pll_dqs_ena_clk) to the c4 port of the PLL: pll_memphy upll_memphy( .areset (~global_reset_n), .inclk0 (pll_ref_clk), .c0 (pll_afi_clk), .c1 (pll_mem_clk), .c2 (pll_write_clk), .c3 (pll_addr_cmd_clk), .c4 (pll_dqs_ena_clk), .c5 (pll_avl_clk), .c6 (pll_config_clk), .locked (pll_locked) );. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] 10.1 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']