CSENT-TX CSENT Transmitter - The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV GX FPGA The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous transmission modes. Under asynchronous mode, the core autonomously, without requiring any extra action from the host system, initiates transmission, as soon as data become available in its input-data register. Under synchronous mode, transmission is triggered by either the host system via the core’s control registers, or when the core receives a valid master trigger pulse via the SENT interface. Designed for ease of use and integration, the core reports its status using two signals, one indicating that a transmission is in progress, and a second one reporting the completion of a frame's transmission. Furthermore, the CSENT-TX provides access to its control, status, and data registers via a 32-bit APB, or an AXI4-Lite or a generic subordinate interface. Implementation of the core is straightforward, as the core contains no latches or tri-states, is fully synchronous with a single clock domain, and includes no multicycle or false paths. The CSENT-TX core is designed with industry best practices, has been rigorously verified and is production proven. Serial Transportation CSENT-TX CSENT Transmitter Key Features SENT/SAE J2716 Transmitter: - Fast & Slow Channel - Choice between 4-bit & 6-bit CRC - Short and Enhanced Messages - Asynchronous/Synchronous modes Offering Brief No Yes No Yes Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi000009cQ17MAE What's Included Verilog/System Verilog, Encrypted Verilog or System Verilog or netlist Ordering Information CSENT-TX a1JUi000009cQ17MAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-07-16T22:42:15.000+0000 The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous transmissions. In asynchronous mode, the core autonomously initiates transmission, as data become available in its input-data register. Under synchronous mode, transmission is triggered by either the host system via the core’s control registers, or when the core receives a valid master trigger pulse via the SENT interface. The core reports its status using two signals, one indicating that a transmission is in progress, and a second one reporting the completion of a frame's transmission. The CSENT-TX also provides access to its registers via a 32-bit APB, or an AXI4-Lite or a generic interface. The core contains no latches or tri-states, is fully synchronous with a single clock domain, and includes no multicycle or false paths. The CSENT-TX core has been rigorously verified and is production proven. Partner Solutions