Why does the JESD204B Intel® FPGA IP Example Design fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices? - Why does the JESD204B Intel® FPGA IP Example Design fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices? Description Due to a known problem in the Intel® Quartus® Prime Pro software versions 19.1 to 19.4, the JESD204B Intel® FPGA IP Example Design may fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. This is due to 2 missing ports if synthesising and 1 missing port if simulating the JESD204B Intel® FPGA IP Example Design. Resolution To work around this problem, follow the steps below: 1. For example design synthesis, add these two ports into " altera_jesd204_ed_RX_TX.sv " located at " //ed_synth " at line 365. { .jtag_avmm_bridge_master_reset_reset (jtag_avmm_rst), .jtag_reset_in_reset_reset_n (1'b1), } 2. For example design simulation, add this port at line 364 into "altera_jesd204_ed_RX_TX.sv" located at "//ed_sim/testbench/models" at line 365. { .jtag_reset_in_reset_reset_n (1'b1), } This problem is fixed starting from the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507706716 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']