Why does SCFIFO almost_empty signal stay high while usedw is larger than almost_empty threshold ? - Why does SCFIFO almost_empty signal stay high while usedw is larger than almost_empty threshold ? Description Due to a problem in the SCFIFO, the almost_empty signal stays "high" even if enough data is written into SCFIFO. This problem only occurs in case of both "Show-ahead mode" used and almost_empty threshold is set to "2". Resolution To work around this issue, perform one of the following actions: Set Normal synchronous FIFO mode instead of Show-ahead synchronous FIFO mode Set the almost empty value to something other than 2 Enable underflow circuitry protection This problem is fixed beginning with the Quartus Prime software version 17.1. Custom Fields values: ['novalue'] Troubleshooting FB: 438765; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 13.1 ['Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']