VHDL-Generated Fileset Can Encounter Synthesis Problems for UniPHY External Memory Interfaces - VHDL-Generated Fileset Can Encounter Synthesis Problems for UniPHY External Memory Interfaces
Description An error in the VHDL-generated wrapper for the synthesis fileset can result in a variety of synthesis problems. Resolution The workaround for this issue is to open the generated wrapper file in a text editor, and replace all ports of the form std_logic_vector(0 downto 0) with std_logic .
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
12.0
11.1
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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