Why do the CSR registers report ECC data errors when the read data is not corrupted? - Why do the CSR registers report ECC data errors when the read data is not corrupted? Description The configuration and status registers (CSR) may report bit errors even though the traffic generator monitor does not detect data corruption when you enable both error correction code (ECC) and CSR in the DDR3 hard memory controller (HMC) MegaWizard™ GUI settings. This discrepancy is seen because the memory controller reads data from uninitialized locations. Resolution The workaround for this issue is to load the memory with known content when you enable the ECC feature. Custom Fields values: ['novalue'] Troubleshooting 1408188506 False ['DDR3 SDRAM Controller with UniPHY IP'] ['novalue'] novalue novalue ['Arria® II GZ FPGA', 'Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']