Why can’t I run RTL simulations of Stratix® 10 FPGA device fPLL VHDL models using Cadence* Xcelium tools? - Why can’t I run RTL simulations of Stratix® 10 FPGA device fPLL VHDL models using Cadence* Xcelium tools? Description The Quartus® Prime software version 18.0 and earlier does not support simulation of the Stratix® 10 FPGA device fPLL using the Cadence* Xcelium simulation tools. Resolution To work around this problem you can use Cadence NCSim® or generate Verilog fPLL simulation models using the Quartus Prime software. Support of fPLL RTL simulation using the Cadence Xcelium tools will be added to a future version of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 556484; False ['L-Tile H-Tile fPLL Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']