Why does the PCIe* DMA Controller Stratix® 10 FPGA IP send two continuous MSI interrupts for the DMA operation? - Why does the PCIe* DMA Controller Stratix® 10 FPGA IP send two continuous MSI interrupts for the DMA operation? Description Due to a problem in the PCIe* DMA Controller Stratix® 10 FPGA IP, the DMA controller will send out two continuous MSI interrupts: one for the DMA Read MSI vector and the other for the DMA Write MSI vector. When either a DMA Read or DMA Write operation completes, if the driver programs the “Write Data Mover Interrupt Control Register”(MSI Address and Vector For DMA Write) and the “Read Data Mover interrupt control register” (MSI Address and Vector For DMA Read), both interrupts will be sent. Resolution To work around this problem, please use the alternative method to send the MSI interrupts by programing the last descriptor of the DMA read or DMA write operation as the MSI Address and MSI Vector. Custom Fields values: ['novalue'] Troubleshooting 1507076280 True ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']