IP Compiler for PCI Express User Guide is Missing Description of lane_act[3:0] Signal - IP Compiler for PCI Express User Guide is Missing Description of lane_act[3:0] Signal Description The IP Compiler for PCI Express User Guide does not describe the lane_act[3:0] signal. The following information is missing from the user guide: Lane active mode: This output signal indicates the number of lanes that configured during link training. This signal has the following valid values: 4’b0001: One lane 4’b0010: Two lanes 4’b0100: Four lanes 4’b1000: Eight lanes Resolution This issue has no workaround. The signal is described in this erratum. This issue will be fixed in a future version of the I P Compiler for PCI Express User Guide . Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']