Why are there missing Hex files when I simulate DDR3 SDRAM Controller with UniPHY? - Why are there missing Hex files when I simulate DDR3 SDRAM Controller with UniPHY? Description Simulating a DDR2 SDRAM or DDR3 SDRAM Controller with UniPHY in version 11.0 controller will result in the following three error messages: # ERROR: cannot read hierarchy _ram_a.hex. # # ERROR: cannot read hierarchy _ram_b.hex. # # ERROR: cannot read hierarchy _ociram_default_contents.hex. # The hex files are missing from the simulation project directory where the simulation is executed. These errors have no effect on simulation and the simulation will still run without any issues. The solution is to copy the hex files from the simulations submodules directory to the simulation project directory. For the controller example design, the simulaton project directory is core _example_design/simulation/simulation/modelsim and the simulation submodules directory is core _example_design/simulation/ core _example_sim/submodules. This issue will be fixed in future version of the Quartus ® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV E FPGA'] ['Simulation Dev Tools ModelSim'] ['novalue'] ['novalue']