Two qsys system in Cyclone V - Two qsys system in Cyclone V hi there, is it possible create a two qsys system (see below system image) with following system components on one fpga? sys1 components: nios ii, onchip mem, spi 3 wire (config as master) sys2 components: nios ii, onchip mem, spi 3 wire (config as slave) and have separate eclipse code for sys1 and sys2. i would like to test this in my DE10 NANO board. i want this setup as a testbench to test my SPI master / slave communication code without buying a another DE10 nano. if its possible, please give me some examples or tutorial link. Replies: Re: Two qsys system in Cyclone V Hi, Do you have any further concern or consideration on this thread? Thanks, Best Regards, Sheng Replies: Re: Two qsys system in Cyclone V Hi, Multi-Nios core processor is possible check this design example link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-multi-nios2-hardware.html and pdf link http://www.ee.nmt.edu/~erives/554_10/Altera_Multiprocessors.pdf Thanks, Best Regards, Sheng