10GBASE-R PHY Setup Time Violation in Arria V GZ Devices with 1588 - 10GBASE-R PHY Setup Time Violation in Arria V GZ Devices with 1588 Description The 10GBASE-R PHY IP Core has a hold time violation in the Arria V Ethernet MAC example design. This timing violation occurs for the fast model. Resolution This issue is fixed in version 13.0 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']