Why do I see an extra read data valid assertion on the Intel® Arria® 10 FPGA EMIF MMR interface? - Why do I see an extra read data valid assertion on the Intel® Arria® 10 FPGA EMIF MMR interface? Description If your Intel® Arria® 10 FPGA memory controller Intel® FPGA IP has the MMR interface enabled, you might notice that the mmr_readdatavalid signal asserts occasionally even when no read commands are issued. The mmr_readdatavalid assertion originates from the memory controller's internal read command and could cause the Avalon® host interface to capture the wrong read data. Resolution The Avalon host interface must only accept mmr_readdatavalid based on the following requirements: mmr_readdatavalid returns one cycle after issuing read request to MMR register ecc1, ecc2, ecc3, ecc4. mmr_readdatavalid returns three cycles after issuing read request to all other MMR registers other than ecc1, ecc2, ecc3, ecc4. Example: The Avalon host interface should only accept mmr_readdatavalid one clock cycle after sending read request to register ecc1 (with mmr_waitrequest signal low). Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']