Error (10476): VHDL error at <VHDL wrapper>.vhd(): type of identifier "reconfig_clk"/"reconfig_reset" does not agree with its usage as "std_logic_vector" type - Error (10476): VHDL error at <VHDL wrapper>.vhd(): type of identifier "reconfig_clk"/"reconfig_reset" does not agree with its usage as "std_logic_vector" type Description You may see this error if you perform an IP upgrade in Quartus® Prime Standard/Pro Edition Software version 17.0 of an Arria® 10 design that includes a static VHDL wrapper that instantiates the JESD204B IP core with transceiver dynamic reconfiguration interface enabled. This is due to the port type change in reconfig_clk and reconfig_reset ports from scalar std_logic to array std_logic_vector. This problem does not affect designs with the Verilog wrapper that instantiates JESD204B IP. Resolution To workaround this problem, map the scalar reconfig_clk & reconfig_reset in the VHDL wrapper to the array reconfig_clk(0) and reconfig_reset(0) of the JESD204B IP core. Example : Before change : port map ( reconfig_clk => reconfig_clk, reconfig_reset => reconfig_reset, reconfig_avmm_address => reconfig_avmm_address, reconfig_avmm_read => reconfig_avmm_read, reconfig_avmm_readdata => reconfig_avmm_readdata, reconfig_avmm_waitrequest => reconfig_avmm_waitrequest, reconfig_avmm_write => reconfig_avmm_write, reconfig_avmm_writedata => reconfig_avmm_writedata, ... After change : port map ( reconfig_clk(0) => reconfig_clk, reconfig_reset(0) => reconfig_reset, reconfig_avmm_address => reconfig_avmm_address, reconfig_avmm_read => reconfig_avmm_read, reconfig_avmm_readdata => reconfig_avmm_readdata, reconfig_avmm_waitrequest => reconfig_avmm_waitrequest, reconfig_avmm_write => reconfig_avmm_write, reconfig_avmm_writedata => reconfig_avmm_writedata, ... This problem is fixed starting with Intel® Quartus® Prime Software version 17.0.1. Custom Fields values: ['novalue'] Troubleshooting FB: 464957; False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 17.0.1 17.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']