Why is my Avalon-MM mode PCI Express core not resetting my logic correctly? - Why is my Avalon-MM mode PCI Express core not resetting my logic correctly? Description When using the Avalon Memory Mapped Interface version of the Hard IP for PCI® Express core, "reset_status" interface signal is "Active Low". NOTE: with Avalon Streaming Interface of Hard IP for PCI Express core, "reset_status" interface signal is "Active High" as stated in the User Guide. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PCI Express'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']