Why do I see timing failures when compiling design with multiple instances of the HDMI Intel® FPGA IP instances - Why do I see timing failures when compiling design with multiple instances of the HDMI Intel® FPGA IP instances Description When using version 20.4 and earlier of the HDMI Intel® FPGA IP timing failures will be seen when compiling a design with multiple instances of the HDMI Intel® FPGA IP. The timing-violated path is related to DCFIFOs. This is due to the auto-generated SDC file failing to cater to multiple instances of the IP. Resolution To work around this problem in version 20.4 and earlier, manually edit the SDC file to account for multiple instances of HDMI Intel® FPGA IP. This problem has been fixed in the 21.1 and later versions of the Intel® Quartus® Prime Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18018336129 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 19.3 ['Arria® V FPGAs and SoCs', 'Agilex™ 7 FPGA F-Series', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']