TSN-SE: TSN Ethernet Switched Endpoint Controller - "The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Networking (TSN) Ethernet networks. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. With cut-through switching and minimal buffering even at the Ethernet MAC level, the TSN-SE features extremely low and deterministic ingress and egress latencies and simplifies the development of time-aware applications. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements, and provides the system with timing information (timestamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint. The TSN-SE uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via AXI-Streaming interfaces with 32-bit data buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as IEEE 802.1Qcc, IEEE 802.1Qca and SNMP, are optionally available Ethernet Aerospace Defense Government Industrial Medical Transportation Wireless TSN-SE: TSN Ethernet Switched Endpoint Controller Key Features 802.1AS-2020 FreeRTOS and Linux gPTP stack Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6cMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog or FPGA netlist Ordering Information TSN-SE Direct a1JUi0000049U6cMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:28.000+0000 "The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing synchronization, 802.1Qav/Qbv traffic shaping, 802.1Qbu/802.3br frame preemption, plus two low-latency Ethernet MACs. Optional modules enable enhanced reliability with 802.1CB frame replication and elimination, and 802.1Qci per-stream filtering and policing. Designed for daisy-chained or ring topologies and bridged endpoints, TSN-SE delivers precise, deterministic ingress/egress latency via cut-through switching and minimal buffering, simplifying time-aware application development. It provides real-time timing data timestamps, alarms, and allows dynamic traffic-shaping configuration. Integration is seamless via standard AMBA® interfaces: a 32-bit APB bus for control/status, and 32-bit AXI-Streaming for packet I/O. Optional DMA engine and software stacks are also available. Partner Solutions