Warning : pcie_link_inspector and JTAG master not found - Warning : pcie_link_inspector and JTAG master not found Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.2 and onward, the following error will occur when performing the PCI Express Link Inspector Debugging tool in L-Tile and H-Tile Avalon® Memory-mapped FPGA IP for PCI Express for Stratix® 10 GX FPGA. Warning: pcie_link_inspector and JTAG master not found error: master_read_32 : Error: The given path is not valid while executing "master_read_32 $slave [expr $base_addr - {$address_hex*4}] 1" (procedure ."pli_read32" line 2) invoked from within "pli_read32 $pli_adne $ltssm_base_addr 0x01" (procedure "ltssm_debug_check" line 2) invoked from within "ltssm_debug_check" (file "TCL/link_insp_test_suite.tcl" line 176) invoked from within "source TCL/link_insp_test_suite.tcl" (file "c:/temporary/tcl/pcie_link_inspector.tcl" line 26) invoked from within "source $PATH/pcie_link_inspector.tcl" Resolution To work around this problem, copy the TCL folder and .sof file from the L-tile and H-tile Avalon® Memory-mapped FPGA IP for PCI Express example to the project directory, then read it as designed. Reboot the system for enumeration. Run the commands below $ source TCL/setup_adme.tcl $ source TCL/xcvr_pll_test_suite.tcl $ source TCL/ltssm_state_monitor.tcl $ source TCL/link_insp_test_suite.tcl $ source TCL/hip_reconfig_display.tcl $ ltssm_display 25 This problem is fixed in Quartus® Prime Pro Edition Software v22.2 during example design generation. Custom Fields values: ['novalue'] Troubleshooting 15011729934 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 22.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']