Design Block Reuse in the Altera® Quartus® Prime Pro Software - 44 Minutes Designing, organizing, and optimizing a single, large FPGA design can be difficult and time consuming. Projects are often divided up into smaller projects that can be worked on by separate team members, for separately testing different parts of the design, or to create reusable design blocks for use in future projects. While doing this is helpful, integrating the work of different team members or reusing parts of a previous design in other projects adds complexity. In this class, you will learn about design block reuse, the ability to partition your design and provide parts of it to other projects or integrate complete or incomplete parts into your project. You’ll see how the tools facilitate this design reuse and sharing model when working with multiple Altera® Quartus Prime projects. Course Objectives At course completion, you will be able to: Set up and perform design block reuse through design partition creation in the Altera® Quartus Prime Pro Edition software Generate design partition compilation database files (.qdb) for use in other projects Integrate complete or incomplete core or root partition designs into a final project Skills Required Basic knowledge of the Altera® Quartus Prime software knowledge of creating FPGA designs in a hardware description language (Verilog or VHDL) Familiarity with design partitioning and device floorplanning with logic Lock regions If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (cc) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OBBDR100. FPGA_OBBDR100. <p>Design Block Reuse in the Altera Quartus Prime Pro Software</p>